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isd 2727 north first street, san jose, ca 95134 tel: 408/943-6666 fax: 408/544-1787 http://www.isd.com a u gu st 2 00 0 figure: isd5008 block diagram aux in amp 1.0/1.414/2.0/2.828 agc sum1 mux vol mux filter mux sum1 fthru inp ana out mux vol sum2 ana in sum2 sp+ sp - speaker aux out ana out - ana out+ mic+ mic - agccap microphone aux in xclk ana in v ssa v cca input source mux filto sum1 inp ana in sum2 filto vol sum1 summing amp ana in amp 0.625/0.883/1.25/1.76 6db sum2 summing amp output mux volume control mic in aux in filto ana in sum1 ana in filto array inp sum1 mux array spkr . amp aux out amp v ssa v ssd v ssd v ccd v ccd device control ana out amp s s 2 ( ) vls0 vls1 2 ( ) aig0 aig1 2 ( ) axg0 axg1 2 ( ) s1s0 s1s1 2 ( ) s1m0 s1m1 2 ( ) s2m0 s2m1 ( ) opa0 opa1 2 ( ) ops0 ops1 2 internal clock multilevel storage array ( ) fld0 fld1 2 (ins0) 1 1 (axpd) 1 (agpd) 1 (flpd) 1 (fls0) 1 (aipd) 1 (aopd) ( ) 3 aos0 aos1 aos2 3 ( ) vol0 vol1 vol2 car kit chip set car kit chip set low pass filter v ssa power conditioning miso mosi ss sclk rac int 1 (vlpd) aux in amp 1.0/1.414/2.0/2.828 agc sum1 mux vol mux filter mux sum1 fthru inp ana out mux vol sum2 ana in sum2 sp+ sp - speaker aux out ana out - ana out+ mic+ mic - agccap microphone aux in xclk ana in v ssa v cca input source mux filto sum1 inp ana in sum2 filto vol sum1 summing amp ana in amp 0.625/0.883/1.25/1.76 6db sum2 summing amp output mux volume control mic in aux in filto ana in sum1 ana in filto array inp sum1 mux array spkr . amp aux out amp v ssa v ssd v ssd v ccd v ccd device control ana out amp s s 2 ( ) vls0 vls1 ( ) vls0 vls1 2 ( ) aig0 aig1 2 ( ) axg0 axg1 2 ( ) s1s0 s1s1 2 ( ) s1m0 s1m1 2 ( ) s2m0 s2m1 ( ) s2m0 s2m1 ( ) opa0 opa1 2 ( ) ops0 ops1 2 internal clock multilevel storage array ( ) fld0 fld1 ( ) fld0 fld1 2 2 (ins0) 1 1 (axpd) 1 (agpd) 1 (flpd) 1 (flpd) 1 (fls0) 1 (aipd) 1 (aopd) ( ) 3 aos0 aos1 aos2 3 3 ( ) vol0 vol1 vol2 ( ) vol0 vol1 vol2 car kit chip set car kit chip set low pass filter v ssa power conditioning miso mosi ss sclk rac int 1 (vlpd) isd5008 product summary the isd5008 chipcorder product is a fully-inte- grated, single-chip solution which provides seam- less integration of enhanced voice record and playback features for digital cellular phones (gsm, cdma, tdma, pdc, and phs), automotive com- munications, gps/navigation systems, and porta- ble communication products. this low-power, 3- volt product enables customers to quickly and easily integrate 4 to 8 minutes of voice storage features such as one-way and two-way (full du- plex) call record, voice memo record, and call screening/answering machine functionality. like other chipcorder products, the isd5008 inte- grates the sampling clock, anti-aliasing and smoothing filters, and the multi-level storage array on a single-chip. for enhanced voice features, the isd5008 eliminates external circuitry by also in- tegrating automatic gain control (agc), a power amplifier/speaker driver, volume control, sum- ming amplifiers, analog switches, and a car kit in- terface. input level adjustable amplifiers are also included, providing a flexible interface for multiple applications. isd5008 single-chip voice record/playback device 4-, 5-, 6-, and 8-minute durations preliminary datasheet
isd5008 product ii voice solutions in silicon ? duration/sample rate selection is accomplished via software, allowing customers to optimize qual- ity and duration for various features within the same end product. the isd5008 device is designed for use in a micro- processor- or microcontroller-based system. ad- dress, control, and duration selection are accomplished through a serial peripheral inter- face (spi) or microwire serial interface to minimize pin count. recordings are stored in on-chip nonvolatile memory cells, providing zero-power message storage. this unique, single-chip solution is made possible through isd?s patented multilevel storage technology. voice and audio signals are stored directly into solid-state memory in their natural, un- compressed form, providing superior quality voice and music reproduction. isd5008 features fully-integrated solution single-chip voice record/playback solution integrated sampling clock, anti-aliasing and smoothing filters, and multi-level storage array integrated analog features such as automatic gain control (agc), audio gating switches, speaker driver (23mw with 8 ohm load), summing amplifiers, volume control, and an aux in/aux out interface (e.g., for car kits). low-power consumption single +3 volt supply operating current: i cc play = 15 ma (typical) i cc rec = 25 ma (typical) i cc feedthru = 12 ma (typical) standby current: i sb = 1 a power consumption controlled by spi or microwire control register most stages can be individually powered down for minimum power consumption enhanced voice features one or two-way (full duplex) conversation record (record signal summation) one- or two-way (full duplex) message playback (while on a call) voice memo record and playback private call screening in-terminal answering machine personalized outgoing message (given caller id information from host chip set) private call announce while on call (given cidcw information from host chip set) easy-to-use and control no compression algorithm development required user-controllable sample rates of 8.0 khz, 6.4 khz, 5.3 khz, or 4.0 khz providing up to 8 minutes of voice storage. microcontroller spi or microwire? serial interface fully addressable to handle multiple messages in 1200 rows high quality solution high quality voice and music reproduction isd?s standard 100-year message retention (typical) 100,000 record cycles (typical) options available in die form, pdip, soic, tsop, and chip scale packaging (csp) compact bga chip scale package available for portable applications extended temperature (-20 to +70c) and industrial temperature (-40 to +85c) versions available
table of contents 1 detailed description ................................................. .................... 1 1.1 speech/sound quality ...................................... .................... 1 1.2 duration ............................................................ .................... 1 1.3 flash storage .................................................... .................... 1 1.4 microcontroller interface .......... ............................................. 1 1.5 programming .................................................... .................... 1 2 pin descriptions ........................................................ .................... 2 2.1 digital i/o pins ................................................... .................... 2 2.2 analog i/o pins .................................................. .................... 3 2.3 power and ground pins .................................... .................... 6 3 internal functional blocks .................................... .................... 7 4 serial peripheral interface (spi) description .......... .................... 13 4.1 message cueing .............................................. .................... 13 4.2 power-up sequence ......................................... .................... 14 4.3 spi port .............................................................. .................... 15 4.4 spi control register ........................................... .................... 15 5 operational modes description ............................. .................... 21 5.1 feed through mode ......................................... .................... 21 5.2 call record ...... ................................................ .................... 23 5.3 memo record ......................... ......................... .................... 24 5.4 memo and call record playback .. .................. .................... 24 6 timing diagrams ....................................................... .................... 34 7 device physical dimensions ..................................... .................... 36 8 ordering information ........................................... .................... 42
isd5008 product 1 isd 1 detailed description 1.1 speech/sound quality the isd5008 chipcorder product can be config- ured via software to operate at 4.0, 5.3, 6.4, and 8.0 khz sampling frequencies, allowing the user a choice of speech quality options. increasing the duration decreases the sampling frequency and bandwidth, which affects sound quality. table 1 compares filter pass band and product durations. the speech samples are stored directly into on-chip nonvolatile memory without the digitization and compression associated with other solutions. di- rect analog storage provides a natural sounding reproduction of voice, music, tones, and sound effects not available with most solid-state solu- tions. 1.2 duration to meet end system requirements, the isd5008 device is a single-chip solution which provides from 4 to 8 minutes of voice record and playback, depending on the sample rates defined by cus- tomer software. 1.3 flash storage one of the benefits of isd?s chipcorder technology is the use of on-chip nonvolatile memory, which pro- vides zero-power message storage. the message is retained for up to 100 years (typically) without power. in addition, the device can be re-record- ed over 100,000 times (typically). 1.4 microcontroller interface a four-wire (sclk, mosi, miso, ss ) spi interface is provided for isd5008 control, addressing func- tions, and sample rate selection. the isd5008 is configured to operate as a peripheral slave de- vice with a microcontroller-based spi bus inter- face. read/write access to all the internal registers occurs through this spi interface. an interrupt sig- nal (int ) and internal read-only status register are provided for handshake purposes. 1.5 programming the isd5008 series is also ideal for playback-only applications, where single or multiple message playback is controlled through the spi port. once the desired message configuration is created, du- plicates can easily be generated via an isd or third-party programmers. for more information on available application tools and programmers please see the isd web site at www.isd.com. table 1: input sample rate to duration input sample rate (khz) duration (minutes) typical filter pass band (khz) 8.0 4.0 3.4 6.4 5.0 2.7 5.3 6.0 2.3 4.0 8.0 1.7
isd5008 product 2 voice solutions in silicon ? 2pin descriptions 2.1 digital i/o pins sclk (serial clock) the sclk is the clock input to the isd5008. gener- ated by the master microcontroller, the sclk syn- chronizes data transfers in and out of the device through the miso and mosi lines. data is latched into the isd5008 on the rising edge of sclk and shifted out on the falling edge. ss (slave select) this input, when low, will select the isd5008 de- vice. mosi (master out slave in) mosi is the serial data input to the isd5008 de- vice. the master microcontroller places data to be clocked into the isd5008 device on the mosi line one-half cycle before the rising edge of sclk. data is clocked into the device lsb (least signifi- cant bit) first. miso (master in slave out) miso is the serial data output of the isd5008 de- vice. data is clocked out on the falling edge of sclk. this output goes into a high-impedance state when the device is not selected. data is clocked out of the device lsb first. int (interrupt) int is an open drain output pin. the isd5008 inter- rupt pin goes low and stays low when an over- flow (ovf) or end of message (eom) marker is detected. each operation that ends in an eom or ovf generates an interrupt, including the mes- sage cueing cycles. the interrupt is cleared the next time an spi cycle is completed. the interrupt status can be read by a rint instruction that will give one of the two flags out the miso line. ovf flag . the overflow flag indicates that the end of the isd5008?s analog memory has been reached during a record or playback operation. eom flag. the end of message flag is set only during playback, when an eom is found. there are eight possible eom markers per row. rac (row address clock) rac is an open drain output pin that marks the end of a row. at the 8 khz sample frequency, the duration of this period is 200 ms. there are 1,200 rows of memory in the isd5008 devices. rac stays high for 175 ms and stays low for the remaining 25 ms before it reaches the end of the row. the rac pin remains high for 109.38 sec and stays low for 15.63 sec under the message cue- ing mode. see table 15 timing parameters for rac timing information at other sample rates. when a record command is first initiated, the rac pin remains high for an extra t raclo period, to load sample and hold circuits internal to the de- vice. the rac pin can be used for message man- agement techniques. xclk (external clock input) the external clock input for the isd5008 product has an internal pull-down device. normally, the isd5008 is operated at one of four internal rates selected for its internal oscillator by the sample rate select bits. if greater precision is required, the device can be clocked through the xclk pin as described in table 2. because the antialiasing and smoothing filters track the sample rate select bits, one must, for optimum performance, change the external clock and the sample rate configuration bits to one of the four values to properly set the filters to the correct cutoff frequency as described in table 3. the duty cycle on the input clock is not critical, as the clock is immediately divided by two inter- nally. if the xclk is not used, this input should be connected to v ssd .
isd5008 product 3 isd table 3: internal clock rate/filter edge 2.2 analog i/o pins mic+, mic ? (microphone input+/?) the microphone input transfers the voice signal to the on-chip agc preamplifier or directly to the ana out mux, depending on the selected path. the direct path to the ana out mux has a gain of 6 db so a 208 mvp-p signal across the differential microphone inputs would give 416 mvp-p across the ana out pins. the agc circuit has a range of 45 db in order to deliver a nominal 694 mvp-p into the storage array from a typical electret micro- phone output of 2 to 20 mvp-p. the input imped- ance is typically 10 k ? figure 1: microphone input table 2: external clock input table duration (minutes) sample rate (khz) required clock (khz) 4 8.0 1024 5 6.4 819.2 6 5.3 682.7 84.0 512 fld1 fld0 sample rate (khz) filter pass band (khz) 00 8 3.4 01 6.4 2.7 10 5.3 2.3 11 4 1.7 r a = 10 k 10 k c coup = 0.1 f 0.1 f internal to the device electret microphone wm-54b panasonic 1.5 k 1.5 k 1.5 k 220 f vcc mic+ mic note: f cutoff = 1 2 r a c coup
isd5008 product 4 voice solutions in silicon ? ana in (analog input) the ana in pin is the analog input from the tele- phone chip set. it can be switched (by the spi bus) to the speaker output, the array input or to various other paths. this pin is designed to accept a nom- inal 1.11 vp-p when at its minimum gain (6 db) setting. there is additional gain available in 3 db steps controlled from the spi bus, if required, up to 15 db. figure 2: ana in input modes 1. gain from ana in to sp+/? 2. gain from ana in to array in 3. 0tlp input is the reference transmission level point that is used for testing. this level is typically 3 db below clipping. 4. speaker out gain set to 1.6 (high). (differential) gain setting resistor ratio (rb/ra) gain gain 2 (db) 00 63.9/102 0.625 ?4.1 01 77.9/88.1 0.88 ?1.1 10 92.3/73.8 1.25 1.9 11 106/60 1.77 4.9 table 4: ana in amplifier gain settings setting (1) 0tlp input v pp (3) cfg0 gain (2) array in/out v pp speaker out v pp (4) aig1 aig0 6 db 1.11 0 0 .625 .694 2.22 9 db .785 0 1 .883 .694 2.22 12 db .555 1 0 1.250 .694 2.22 15 db .393 1 1 1.767 .694 2.22
isd5008 product 5 isd aux in (auxiliary input) the aux in is an additional audio input to the isd5008, such as from the microphone circuit in a mobile phone ?car kit.? this input has a nominal 700 mvp-p level at its minimum gain setting (0 db). see table 5. additional gain is available in 3 db steps (controlled by the spi bus) up to 9 db. figure 3: aux in input modes 1. gain from aux in to ana out 2. gain from aux in to array in 3. 0tlp input is the reference transmission level point that is used for testing. this level is typically 3 db below clipping. 4. differential gain setting resistor ratio (rb/ra) gain gain (db) 00 40.1/40.1 1.0 0 01 47.0/33.2 1.414 3 10 53.5/26.7 2.0 6 11 59.2/21 2.82 9 table 5: auxin amplifier gain settings setting (1) 0tlp input v pp (3) cfg0 gain (2) array in/out v pp ana out v pp (4) axg1 axg0 0 db .694 0 0 1.00 .694 .694 3 db .491 0 1 1.41 .694 .694 6 db .347 1 0 2.00 .694 .694 9 db .245 1 1 2.82 .694 .694
isd5008 product 6 voice solutions in silicon ? anaout+/? (analog outputs) this differential output is designed to go to the mi- crophone input of the telephone chip set. it is de- signed to drive a minimum of 5 k ? not ground the unused pin. aux out (auxiliary output) the auxout is an additional audio output pin, to be used, for example, to drive the speaker circuit in a ?car kit.? it drives a minimum load of 5 k ? sp+, sp? (speaker+/?) this is the speaker differential output circuit. it is de- signed to drive an 8 ? not ground the unused pin. acap (agc capacitor) this pin provides the capacitor connection for setting the parameters of the microphone agc circuit. it should have a 4.7 f capacitor con- nected to ground. it cannot be left floating. this is because the capacitor is also used in the playback mode for the automute circuit. this circuit reduces the amount of noise present in the output during quiet pauses. tying this pin to ground gives maximum gain; to v cca gives minimum gain for the agc amplifier but will cancel the automute function. 2.3 power and ground pins v cca , v ccd (voltage inputs) to minimize noise, the analog and digital circuits in the isd5008 device uses separate power bus- ses. these +3 v busses lead to separate pins. tie the v ccd pins together as close as possible and decouple both supplies as near to the package as possible. v ssa , v ssd (ground inputs) the isd5008 series utilizes separate analog and digital ground busses. the analog ground (v ssa ) pins should be tied together as close to the pack- age as possible and connected through a low- impedance path to power supply ground. the digital ground (v ssd ) pin should be connected through a separate low-impedance path to pow- er supply ground. these ground paths should be large enough to ensure that the impedance be- tween the v ssa pins and the v ssd pin is less than 3 ?
isd5008 product 7 isd figure 4: isd5008 series tsop and pdip/soic pinouts 3 internal functional blocks figure 5: microphone amplifier 28-pin tsop isd5008 pdip/soic isd5008 microphone (300 mvp-p max) mic+ mic? acap fthru agc 1 (agpd) 6 db to automute (playback only) * * differential path agpd 0 power up 1 power down 1514131211109876543210 vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd cfg1 agc
isd5008 product 8 voice solutions in silicon ? figure 6: aux in and ana in car kit aux in aux in amp aux in 1514131211109876543210 aig1 aig0 aipd axg1 axg0 axpd ins0 aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd cfg0 amp 1.0 / 1.414 / 2.0 / 2.828 1 (axpd) axpd 0 power up 1 power down 2 (axg1, axg0) axg1 axg0 input gain 0tlp input level 0 0 1 .694 0 1 1.414 .491 1 0 2 .347 1 1 2.828 .245 chip set ana in ana in amp ana in amp .625 /.883 / 1.25 / 1.767 1 (aipd) aipd 0 power up 1 power down 2 (aig1,aig0) aig1 aig0 input gain 0tlp input level 000.6251.11 010.883.785 101.250.555 111.767.393
isd5008 product 9 isd figure 7: isd5008 core (left half) input agc amp sum1 s1m1 s1m0 source 00both 0 1 sum1 mux only 10inp only 11power down source mux sum1 summing amp 1514131211109876543210 aig1 aig0 aipd axg1 axg0 axpd ins0 aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd cfg0 aux in amp filto sum1 mux ana in amp array 2 (s1s1,s1s0) s1s1 s1s0 source 0 0 ana in amp 01array 10filto 11n/c 1514131211109876543210 vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd cfg1 inso source 0agc amp 1aux in amp (ins0)
isd5008 product 10 voice solutions in silicon ? figure 8: isd5008 core (right half) sum1 sum2 s2m1 s2m0 source 00both 01ana in only 1 0 filto only 11power down filter mux sum2 summing amp array 2 fld1 fld0 sample rate filter pass band 008khz 3.4 khz 0 1 6.4 khz 2.7 khz 1 0 5.3 khz 2.3 khz 114 khz 1.7 khz 1514131211109876543210 vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd cfg1 filto low pass filter internal clock multilevel storage array fls0 source 0sum1 1 array 1 (fls0) 1 (flpd) flpd 0 power up 1 power down array ana in amp xclk (fld1,fld0)
isd5008 product 11 isd figure 9: volume control ins0 vol 1514131211109876543210 aig1 aig0 aipd axg1 axg0 axpd aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd cfg0 sum2 vol mux sum1 inp 2 vls1 vls0 source 00ana in amp 01sum2 10sum1 11inp 1514131211109876543210 vls1 vls0 vol2 vol1 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 fls0 fld1 fld0 flpd agpd cfg1 ana in amp volume control (vls1,vls0) 3 vol2 vol1 vol0 attenuation 0000 db 0014 db 0108 db 0 1 1 12 db 1 0 0 16 db 1 0 1 20 db 1 1 0 24 db 1 1 1 28 db (vol2,vol1,vol0) 1 (vlpd) vlpd 0 power up 1 power down vol0
isd5008 product 12 voice solutions in silicon ? figure 10: speaker and aux out figure 11: ana out output speaker sp+ sp? aux out car kit (1 vp-p max) ana in amp output mux filto sum2 2 ops1 ops0 source 00vol 01ana in 10filto 11sum2 vol (ops1,ops0) 2 opa1 opa0 spkr drive aux op 0 0 power down power down 0 1 3.6 vp-p @ 150 ? ? ? ops1 ops0 opa1 opa0 vlpd cfg0 chip set ana out+ ana out? *vol ana out mux *filto *sum2 3 (aos2,aos1,aos0) aos2 aos1 aos0 000fthru 001inp 010vol 011filto 100sum1 101sum2 110n/c 111n/c *fthru 1 aopd 0 power up 1 power down (aopd) ins0 1514131211109876543210 aig1 aig0 aipd axg1 axg0 axpd aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd cfg0 *inp *sum1 (1 vp-p max. from aux in or array) (600 mvp-p max. from microphone input) *differential path
isd5008 product 13 isd 4 serial peripheral interface (spi) description the isd5008 product operates from an spi serial in- terface. the spi interface operates with the following protocol. the data transfer protocol assumes that the mi- crocontroller?s spi shift registers are clocked on the falling edge of the sclk. with the isd5008, data is clocked in on the mosi pin on the rising clock edge. data is clocked out on the miso pin on the falling clock edge. 1. all serial data transfers begin with the falling edge of ss pin. 2. ss is held low during all serial communica- tions and held high between instructions. 3. data is clocked in on the rising clock edge and data is clocked out on the falling clock edge. 4. play and record operations are initiated by enabling the device by asserting the ss pin low, shifting in an opcode and an address field to the isd5008 device (refer to the op- code summary on the page 14). 5. the opcodes and address fields are as fol- lows: <8 control bits> and <16 address bits>. 6. each operation that ends in an eom or overflow will generate an interrupt, includ- ing the message cueing cycles. the inter- rupt will be cleared the next time an spi cycle is completed. 7. as interrupt data is shifted out of the isd5008 miso pin, control and address data is simultaneously being shifted into the mosi pin. care should be taken such that the data shifted in is compatible with current system operation. it is possible to read interrupt data and start a new opera- tion within the same spi cycle. 8. a record or playback operation begins with the run bit set and the operation ends with the run bit reset. 9. all operations begin with the rising edge of ss . 4.1 message cueing message cueing allows the user to skip through messages, without knowing the actual physical lo- cation of the message. this operation is used dur- ing playback. in this mode, the messages are skipped 1600 times faster than in normal play- back mode. it will stop when an eom marker is reached. then, the internal address counter will point to the next message.
isd5008 product 14 voice solutions in silicon ? 1. x = don?t care. 2. changes in cfg0 are not recognized until cfg1 is loaded. the changes will occur at the rising edge of ss during the cycle that cfg1 is loaded. 4.2 power-up sequence the isd5008 will be ready for an operation after t pud (25 ms approximately for 8 khz sample rate). the user needs to wait t pud before issuing an opera- tional command. for example, to play from ad- dress 00 the following programing cycle should be used. playback mode 1. send powerup command. 2. wait t pud (power-up delay). 3. load cfg0 and cfg1 for desired opera- tion. 4. send setplay command with address 00. the device will start playback at address 00 and it will generate an interrupt when an eom is reached. it will then stop playback. record mode 1. send powerup command. 2. wait t pud (power-up delay). 3. load cfg0 and cfg1 for desired opera- tion. 4. send setrec command with address 00. the device will start recording at address 00 and it will generate an interrupt when an overflow is reached (end of memory array) or when it has re- ceived a stop command. it will then stop record- ing. table 6: opcode summary instruction opcode <8 bits> (1) address <16 bits> operational summary powerup 0110 0000 power-up: see ?power-up sequence? loadcfg0 (2) 01x0 0010 loads a 16-bit value into configuration register 0 loadcfg1 01x0 0100 loads a 16-bit value into configuration register 1 setplay 1110 0000 initiates playback from address play 1111 0000 playback from current address (until eom or ovf) setrec 1010 0000 initiates record at address rec 1011 0000 records from current address until ovf is reached mc 1111 1000 performs a message cue. proceeds to the end of the current message (eom) or enters ovf condition if it reaches the end of the array. stop 0111 0000 stops current operation stopwrdn 0101 0000 stops current operation and enters stand-by (power-down) mode. rint 0111 0000 read interrupt status bits: ovf and eom.
15 isd5008 product isd 4.3 spi port the following diagram describes the spi port and the control bits associated with it. figure 12: spi port note: bytes 1 and 2 of the mosi input may be address bits or configuration bits, depending on the selected mode in byte 3. 4.4 spi control register the spi control register provides control of individual device functions such as play, record, message cueing, power-up and power-down, start and stop operations, ignore address pointers and load con- figuration registers. table 7: spi control register control register bit device function control register bit device function run enable or disable an operation pu master power control = = 1 0 start stop = = 1 0 power-up power-down p/r selects play or record operation iab ignore address control bit = = 1 0 play record = = 1 0 ignore input address register (a15?a0) use the input address register contents for an operation (a15?a0) mc enable or disable message cueing a15?a0 output of the row pointer register = = 1 0 enable message cueing disable message cueing d15?d0 input control and address register lc0 lc1 = = 1 0 load configuration reg 0 no load = = 1 0 load configuration reg 1 no load
16 isd5008 product voice solutions in silicon? note: see details on following pages. table 8: configuration register 0 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cfg0 aig1 aig0 aipd axg1 axg0 axpd ins0 aos2 aos1 aos0 aopd ops1 ops0 opa1 opa0 vlpd ana in amp gain set (2 bits) ana in power down aux in amp gain set (2 bits) aux in power down input source mux select (1 bit) ana out mux select (3 bits) ana out power down ouput mux select (2 bits) spkr & aux out control (2 bits) volume control power down note: see details on following pages. table 9: configuration register 1 d15 d14 d13 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 cfg1 vls1 vls0 vol2 vol1 vol0 s1s1 s1s0 s1m1 s1m0 s2m1 s2m0 flso fld1 fld0 flpd agpd volume cont. mux select (2 bits) volume control (3 bits) sum 1 mux select (2 bits) sum 1 summing amp control (2 bits) sum2 summing amp control (2 bits) filter mux select sample rate (& filter) set up (2 bits) filter power down agc amp power down
17 isd5008 product isd detail of configuration register 0 volume control power bit bit 0 (vlpd) 0 = power on 1 = power off speaker and aux out control bits bits 2,1 (opa1, opa0) 00 = power down spkr and aux 01 = spkr on, high gain, aux power down 10 = spkr on, low gain, aux power down 11 = spkr powered down, aux on output mux control bits bits 4,3 (ops1, ops0) 00 = source is vol control (vol) 01 = source is ana in input (ana in amp) 10 = source is low pass filter (filt0) 11 = source is sum2 summing amp (sum2) ana out power bit bit 5 (aopd) 0 = power on 1 = power off ana out mux con- trol bits bits 8,7,6 (aos2, aos1, aos0) 000 = source is microphone amp (fthru) 001 = source is input mux (inp) 010 = source is volume control (vol) 011 = source is low pass filter (filt0) 100 = source is sum1 summing amp (sum1) 101 = source is sum2 summing amp (sum2) 110 = unused 111 = unused input source mux control bit bit 9 (ins0) 0 = source is microphone agc amp (agc) 1 = source is aux in input (aux in amp) aux in amp power bit bit 10 (axpd) 0 = power on 1 = power off aux in amp control bits bits 12,11 (axg1, axg0) 00 = input gain = 1, o tlp input level = 0.694 01 = input gain = 1.414, o tlp input level = 0.491 10 = input gain = 2, o tlp input level = 0.347 11 = input gain = 2.828, o tlp input level = 0.245 ana in amp power bit bit 13 (aipd) 0 = power on 1 = power off ana in amp control bits bits 15,14 (aig1, aig0) 00 = input gain = 0.625, o tlp input level = 1.11 01 = input gain = 0.883, o tlp input level = 0.7l85 10 = input gain = 1.250, o tlp input level = 0.555 11 = input gain = 1.767, o tlp input level = 0.393
18 isd5008 product voice solutions in silicon? configuration register notes 1. important: all changes to the internal settings of the isd5008 are synchronized with the load of configuration register 1. a command to load configuration register 1 immediately transfers the input data to the internal settings of the device and the changes take place immediately at the end of the command when ss\ goes high. a load to configuration register 0 sends the new data to a temporary register in the isd5008 and does not affect the internal settings of the device. the next time configuration register 1 is loaded, data will also transfer from the temporary register to the configuration 0 register and effect the desired changes. see figure table 13. 2. configuration registers may be loaded with data at any time, including when the chip is powered down using the pu bit in the spi control register. the pu bit in the spi control word will have to be set to a ?1? before the changes in configuration will be seen. detail of configuration register 1 agc power control bit bit 0 (agpd) 0 = power on 1 = power off low pass filter power control bit bit 1 (flpd) 0 = power on 1 = power off sample rate and low pass filter control bits bits 3,2 (fld1, fld0) 00 = sample rate = 8 khz, fpb = 3.4 khz 01 = sample rate = 6.4 khz, fpb = 2.7 khz 10 = sample rate = 5.3 khz, fpb = 2.3 khz 11 = sample rate = 4 khz, fpb = 1.7 khz filter mux control bits bit 4 (fls0) 0 = source is sum1 summing amp (sum1) 1 = source is analog memory array (array) sum 2 summing amp control bits bits 6,5 (s2m1, s2m0) 00 = source is both ana in amp and filt0 01 = source is ana in input (ana in amp) only 10 = source is low pass filter (filt0) only 11 = power down sum2 summing amp sum1 summing amp control bits bit 8,7 (s1m1, s1m0) 00 = source is both sum1 and inp 01 = source is sum1 summing amp (sum1) only 10 = source is input mux (inp) only 11 = power down sum1 summing amp sum1mux control bits bit 10,9 (s1s1, s1s0) 00 = source is ana in input (ana in amp) 01 = source is analog memory array (array) 10 = source is low pass filter (filt0) 11 = unused volume control control bits bits 13,12,11 (vol2, vol1, vol0) 000 = attenuation = 0 db 001 = attenuation = 4 db 010 = attenuation = 8 db 011 = attenuation = 12 db 100 = attenuation = 16 db 101 = attenuation = 20 db 110 = attenuation = 24 db 111 = attenuation = 28 db vol mux control bits bit 15,14 (vls1, vls0) 00 = source is ana in input (ana in amp) 01 = source is sum2 summing amp (sum2) 10 = source is sum1 summing amp (sum1) 11 = source is input mux (inp)
isd5008 product 19 isd figure 13: configuration register programming sequence figure 14: spi interface simplified block diagram 1. see table 8 for bit details. { command = load configuration register 1 } command = load configuration register 0 temporary register configuration register 1 configuration register 0 input shift register (16 bits) mosi control word (c7-c0) { command = load configuration register 1 } command = load configuration register 0 temporary register configuration register 1 configuration register 0 input shift register (16 bits) mosi control word (c7-c0) configuration registers (1) d15 d15 d0 d0 cfg1 cfg0 d15 - d0
isd5008 product 20 voice solutions in silicon ? figure 15: typical digital cellular phone integration rf section flash dsp if interface microcontroller keypad display eeprom voice band codec microphone earpiece ana out+ ana out- ana in isd5008 sp+ sp? mic+ mic- spi mic in+ mic in? sp out+ sp out ? aux in aux out car kit spi
isd5008 product 21 isd 5 operational modes description the isd5008 can operate in many different modes. it?s flexibility allows the user to configure the chip such that almost any input can mixed with any other input and then be directed to any output. the variable settings for the ana and aux input amplifiers plus the microphone agc and speaker volume controls make it possible to use the device with most existing cell phone or cord- less phone chip sets with no external level adjust- ment. several modes will be found in most applications, however. please refer to the isd5008 block diagram to better understand the following modes. in all cases, we are assuming that the chip has been powered up with the pu bit in the spi control register and that a time period of t pud has elapsed after that bit was set: 5.1 feed through mode this mode enables the isd5008 to connect to a base band cell phone or cordless phone chip set without affecting the audio source or destination. there are two paths involved, the transmit path and the receive path. the transmit path connects the isd chip?s microphone source through to the microphone input on the base band chip set. the receive path connects the base band chip set?s speaker output through to the speaker driver on the isd chip. this allows the isd chip to substitute for those functions and incidentally gain access to the audio to and from the base band chip set. figure 15 shows one possible connection to such a chip set. figure 16 shows the part of the isd5008 block dia- gram that is used in feed through mode. the rest of the chip will be powered down to conserve power. the bold lines highlight the audio paths. note that the microphone to ana out +/? path is differential. figure 16: basic feed-thru mode chip set ana out+ ana out? vol ana out mux filto sum2 3 (aos2,aos1,aos0) fthru 1 (aopd) inp sum1 speaker sp+ sp? ana in amp output mux filto sum2 2 vol (ops1,ops0) 2 (opa1, opa0) chip set ana in ana in amp .625 /.883 / 1.25 / 1.767 1 (aipd) 2 (aig1,aig0) microphone mic+ mic? 6 db
isd5008 product 22 voice solutions in silicon ? to select this mode, the following control bits must be configured in the isd5008 configuration regis- ters. to set up the transmit path: 1. select the fthru path through the ana out mux? bits aos0, aos1 and aos2 control the state of the anaout mux. these are the d6, d7 and d8 bits respectively of configu- ration register 0 (cfg0) and they should all be zero to select the fthru path. 2. power up the ana out amplifier ?bit aopd controls the power up state of ana out. this is bit d5 of cfg0 and it should be a zero to power up the amplifier. to set up the receive path: 1. set up the ana in amplifier for the correct gain ?bits aig0 and aig1 control the gain settings of this amplifier. these are bits d14 and d15 respectively of cfg0. the input level at this pin determines the setting of this gain stage. table 4 will help determine this setting. in this example we will assume that the peak signal never goes above 1 volt p-p single ended. that would enable us to use the 9db attenuation setting, or where d14 is one and d15 is zero. 2. power up the ana in amplifier ?bit aipd controls the power up state of ana in. this is bit d13 of cfg0 and should be a zero to power up the amplifier. 3. select the ana in path through the output mux ?bits ops0 and ops1 control the state of the output mux. these are bits d3 and d4 respectively of cfg0 and they should be set to the state where d3 is one and d4 is zero to select the ana in path. 4. power up the speaker amplifier ?bits opa0 and opa1 control the state of the speaker and aux amplifiers. these are bits d1 and d2 respectively of cfg0. they should be set to the state where d1 is one and d2 is zero. this powers up the speaker amplifier and configures it for it?s higher gain setting for use with a piezo speaker element and also powers down the aux output stage. the status of the rest of the functions in the isd5008 chip must be defined before the configuration registers settings are updated: 1. power down the volume control ele- ment ?bit vlpd controls the power up state of the volume control. this is bit d0 of cfg0 and it should be set to a one to power down this stage. 2. power down the aux in amplifier ?bit axpd controls the power up state of the aux in input amplifier. this is bit d10 of cfg0 and it should be set to a one to pow- er down this stage. 3. power down the sum1 and sum2 mixer amplifiers ?bits s1m0 and s1m1 control the sum1 mixer and bits s2m0 and s2m1 control the sum2 mixer. these are bits d7 and d8 in cfg1 and bits d5 and d6 in cfg1 respectively. all 4 bits should be set to a one to power down these two amplifi- ers. 4. power down the filter stage ?bit flpd controls the power up state of the filter stage in the device. this is bit d1 in cfg1 and should be set to a one to power down the stage. 5. power down the agc amplifier ?bit agpd controls the power up state of the agc amplifier. this is bit d0 in cfg1 and should be set to a one to power down this stage. 6. don?t care bits ?the following stages are not used in feed through mode. their bits may be set to either level. in this example we will set all the following bits to a zero. (a). bit ins0, bit d9 of cfg0 controls the in- put source mux. (b). bits axg0 and axg1 are bits d11 and d12 respectively in cfg0. they control the aux in amplifier gain set- ting. (c). bits fld0 and fld1 are bits d2 and d3 respectively in cfg1. they control the sample rate and filter band pass setting. (d). bit fls0 is bit d4 in cfg1. it controls the filter mux. (e). bits s1s0 and s1s1 are bits
isd5008 product 23 isd d9 and d10 of cfg1. they control the sum1 mux. (f). bits vol0, vol1 and vol2 are bits d11, d12 and d13 of cfg1. they control the setting of the volume control. (g). bits vls0 and vls1 are bits d14 and d15 of cfg1. they control the volume control mux. the end result of the above set up is cfg0=0100 0100 0000 1011 (hex 440b) and cfg1=0000 0001 1110 0011 (hex 01e3). since both registers are being loaded, cfg0 is loaded followed by the loading of cfg1. these two registers must be loaded in this order. the in- ternal set up for both registers will take effect syn- chronously with the rising edge of ss . 5.2 call record the call record mode adds the ability to record the incoming phone call. in most applications, the isd5008 would first be set up for feed through mode as described above. when the user wishes to record the incoming call, the set up of the chip is modified to add that ability. for the purpose of this explanation, we will use the 6.4 khz sample rate during recording. the block diagram of the isd5008 shows that the multilevel storage array is always driven from the sum2 summing amplifier. the path traces back from there through the low pass filter, the filter mux, the sum1 summing amplifier, the sum1 mux, then from the ana in amplifier. feed through mode has already powered up the ana in amp so we only need to power up and enable the path to the multilevel storage array from that point: 1. select the ana in path through the sum1 mux ?bits s1s0 and s1s1 control the state of the sum1 mux. these are bits d9 and d10 respectively of cfg1 and they should be set to the state where both d9 and d10 are zero to select the ana in path. 2. select the sum1 mux input (only) to the s1 summing amplifier ?bits s1m0 and s1m1 control the state of the sum1 summing amplifier. these are bits d7 and d8 respec- tively of cfg1 and they should be set to the state where d7 is one and d8 is zero to se- lect the sum1 mux (only) path. 3. select the sum1 summing amplifier path through the filter mux ?bit fls0 controls the state of the filter mux. this is bit d4 of cfg1 and it must be set to zero to select the sum1 summing amplifier path. 4. power up the lowpass filter ?bit flpd controls the power up state of the lowpass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 5. select the 6.4 khz sample rate ?bits fld0 and fld1 select the low pass filter set- ting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 6.4 khz sample rate, d2 must be set to one and d3 set to zero. 6. select the low pass filter input (only) to the s2 summing amplifier ?bits s2m0 and s2m1 control the state of the sum2 summing amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to select the low pass filter (only) path. in this mode, the elements of the original pass through mode do not change. the sections of the chip not required to add the record path re- main powered down. in fact, cfg0 does not change and remains cfg0=0100 0100 0000 1011 (hex 440b). cfg1 changes to cfg1=0000 0000 1100 0101 (hex 00c5). since cfg0 is not changed, it is only necessary to load cfg1. note that if only cfg0 was changed, it would be necessary to load both registers.
isd5008 product 24 voice solutions in silicon ? 5.3 memo record the memo record mode sets the chip up to record from the local microphone into the chip?s multilevel storage array. a connected cellular telephone or cordless phone chip set may remain powered down and is not active in this mode. the path to be used is microphone input to agc am- plifier, then through the input source mux to the sum1 summing amplifier. from there the path goes through the filter mux, the low pass filter, the sum2 summing amplifier, then to the multi- level storage array. in this instance, we will se- lect the 5.3 khz sample rate. the rest of the chip may be powered down. 1. power up the agc amplifier ?bit agpd controls the power up state of the agc amplifier. this is bit d0 of cfg1 and must be set to zero to power up this stage. 2. select the agc amplifier through the input source mux ?bit ins0 controls the state of the input source mux. this is bit d9 of cfg0 and must be set to a zero to select the agc amplifier. 3. select the input source mux (only) to the s1 summing amplifier ?bits s1m0 and s1m1 control the state of the sum1 summing amplifier. these are bits d7 and d8 respectively of cfg1 and they should be set to the state where d7 is zero and d8 is one to select the input source mux (only) path. 4. select the sum1 summing amplifier path through the filter mux ?bit fls0 controls the state of the filter mux. this is bit d4 of cfg1 and it must be set to zero to select the sum1 summing amplifier path. 5. power up the lowpass filter? bit flpd controls the power up state of the lowpass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 6. select the 5.3 khz sample rate ?bits fld0 and fld1 select the low pass filter setting and sample rate to be used during record and playback. these are bits d2 and d3 of cfg1. to enable the 5.3 khz sample rate, d2 must be set to zero and d3 set to one. 7. select the low pass filter input (only) to the s2 summing amplifier ?bits s2m0 and s2m1 control the state of the sum2 summing amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to select the low pass filter (only) path. to set up the chip for memo record, the configu- ration registers are set up as follows: cfg0=0010 0100 0010 0001 (hex 2421). cfg1=0000 0001 0100 1000 (hex 0148). only those portions necessary for this mode are powered up. 5.4 memo and call playback this mode sets the chip up for local playback of messages recorded earlier. the playback path is from the multilevel storage array to the filter mux, then to the low pass filter stage. from there the audio path goes through the sum2 sum- ming amplifier to the volume mux, through the volume control then to the speaker output stage. we will assume that we are driving a pizeo speaker element. this audio was previously re- corded at 8 khz. all unnecessary stages will be powered down. 1. select the multilevel storage array path through the filter mux ?bit fls0, the state of the filter mux. this is bit d4 of cfg1 and must be set to one to select the multilevel storage array. 2. power up the lowpass filter ?bit flpd controls the power up state of the lowpass filter stage. this is bit d1 of cfg1 and it must be set to zero to power up the low pass filter stage. 3. select the 8.0 khz sample rate ?bits fld0 and fld1 select the low pass filter setting and sample rate to be used during record
isd5008 product 25 isd and playback. these are bits d2 and d3 of cfg1. to enable the 8.0 khz sample rate, d2 and d3 must be set to zero. 4. select the low pass filter input (only) to the s2 summing amplifier ?bits s2m0 and s2m1 control the state of the sum2 sum- ming amplifier. these are bits d5 and d6 respectively of cfg1 and they should be set to the state where d5 is zero and d6 is one to select the low pass filter (only) path. 5. select the sum2 summing amplifier path through the volume mux ?bits vls0 and vls1 control the state volume mux. these bits are bits d14 and d15, re- spectively of cfg1. they should be set to the state where d14 is one and d15 is zero to select the sum2 summing amplifier. 6. power up the volume control level ? bit vlpd controls the power-up state of the volume control attenuator. this is bit d0 of cfg0. this bit must be set to a zero to power-up the volume control. 7. select a volume control level ?bits vol0, vol1, and vol2 control the state of the volume control level. these are bits d11, d12, and d13, respectively, of cfg1. a binary count of 000 through 111 controls the amount of attenuation through that state. in most cases, the software will select an attenuation level according to the de- sires of the current users of the product. in this example, we will assume the user wants an attenuation of ?12 db. for that setting, d11 should be set to one, d12 should be set to one, and d13 should be set to a ze- ro. 8. select the volume control path through the output mux? these are bits d3 and d4, respectively, of cfg0. they should be set to the state where d3 is zero and d4 is a zero to select the volume control. 9. power up the speaker amplifier and se- lect the high gain mode ?bits opa0 and opa1 control the state of the speaker (sp+ and sp?) and aux out outputs. these are bits d1 and d2 of cfg0. they must be set to the state where d1 is one and d2 is zero to power-up the speaker outputs in the high gain mode and to power-down the aux out. to set up the chip for memo or call playback, the configuration registers are set up as follows: cfg0=0010 0100 0010 0010 (hex 2422). cfg1=0101 1001 1101 0001 (hex 59d1). only those portions necessary for this mode are powered up.
26 isd5008 product voice solutions in silicon? 1. stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functional operation is not implied at these conditions. 1. stresses above those listed may cause permanent damage to the device. exposure to the absolute maximum ratings may affect device reliability. functional operation is not implied at these conditions. 1. case temperature 2. v cc = v cca = v ccd 3. v ss = v ssa = v ssd 1. v cc = v cca = v ccd 2. v ss = v ssa = v ssd table 10: absolute maximum ratings (packaged parts) (1) condition value junction temperature 150c storage temperature range ?65c to +150c voltage applied to any pin (v ss ? 0.3 v) to (v cc + 0.3 v) voltage applied to mosi, sclk, int , rac and ss pins (input current limited to 20ma) (v ss ? 1.0 v) to 5.5v lead temperature (soldering ? 10 seconds) 300c v cc ? v ss ?0.3 v to +7.0 v table 11: absolute maximum ratings (die) (1) condition value junction temperature 150c storage temperature range ?65c to +150c voltage applied to mosi, sclk, int , rac and ss pins (input current limited to 20ma) (v ss ? 0.3 v) to 5.5v v cc ? v ss ?0.3 v to +7.0 v table 12: operating conditions (packaged parts) condition value commercial operating temperature range (1) 0c to +70c extended operating temperature (1) ?20c to +70c industrial operating temperature (1) ?40c to +85c supply voltage (v cc ) (2) +2.7 v to +3.3 v ground voltage (v ss ) (3) 0 v table 13: operating conditions (die) condition value commercial operating temperature range 0c to +50c supply voltage (v cc ) (1) +2.7 v to +3.3 v ground voltage (v ss ) (2) 0 v
27 isd5008 product isd 1. typical values: t a = 25c and vcc = 3.0 v. 2. all min/max limits are guaranteed by isd via electrical testing or characterization. not all specifications are 100 percent tested. 3. v cca and v ccd summed together. 4. ss = v cca = v ccd, xclk = mosi = v ssa = v ssd and all other pins floating. table 14: general parameters symbol parameters min(2) typ(1) max(2) units conditions v il input low voltage v cc x0.2 v v ih input high voltage v cc x0.8 v v ol output low voltage 0.4 v i ol = 10 a v ol1 rac, int output low voltage 0.4 v i ol = 1 ma v oh output high voltage v cc ?0.4 v i oh = ?10 a i cc v cc current (operating) ? playback ? record ? feedthru 15 25 12 ma ma ma no load (3) no load (3) no load (3) i sb v cc current (standby) 1 10 a (3) (4) i il input leakage current 1 a i hz miso tristate current 1 10 a
28 isd5008 product voice solutions in silicon? table 15: timing parameters symbol characteristic min (2) typ (1) max (2) units conditions f s sampling frequency 8.0 6.4 5.3 4.0 khz khz khz khz (5) (5) (5) (5) f cf filter pass band 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 3.4 2.7 2.3 1.7 khz khz khz khz 3-db roll-off point (3) (7) 3-db roll-off point (3) (7) 3-db roll-off point (3) (7) 3-db roll-off point (3) (7) t rec record duration 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 4 5 6 8 min min min min (6) (6) (6) (6) t play playback duration 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 4 5 6 8 min min min min (6) (6) (6) (6) t pud power-up delay 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 25 31.25 37.5 50 msec msec msec msec t stop or pause stop or pause record or play 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 50 62.5 75 100 msec msec msec msec t rac rac clock period 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 200 250 300 400 msec msec msec msec (9) (9) (9) (9) t raclo rac clock low time 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 25 31.25 37.5 50 msec msec msec msec
29 isd5008 product isd t racm rac clock period in message cueing mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 125 156.3 187.5 250 sec sec sec sec t racml rac clock low time in message cueing mode 8.0 khz (sample rate) 6.4 khz (sample rate) 5.3 khz (sample rate) 4.0 khz (sample rate) 15.63 19.53 23.44 31.25 sec sec sec sec thd total harmonic distortion ana in to array, array to spkr 12% @1 khz at 0tlp, sample rate = 5.3khz table 16: analog parameters symbol characteristic min (2) typ (1) max (2) units conditions microphone input (14) v mic+/? mic +/? input voltage 3 300 mv peak-to-peak (4)(8) v mic (0tlp) mic +/? input reference transmission level point (0tlp) 208 mv peak-to-peak (4)(10) a mic gain from mic+/? input to ana out 5.5 6.0 6.5 db 1khz at v mic (0tlp) (4) a mic (gt) mic +/? gain tracking 0.1 db 1 khz, +3 to ?40 db 0tlp input r mic microphone input resistance 51015 k ? mic? and mic+ pins a agc microphone agc amplifier range 640db over 3?300 mv input range ana in (14) v ana in ana in input voltage 1.6 v peak-to-peak (6db gain setting) v ana in (0tlp) ana in (0tlp) input voltage 1.11 v peak-to-peak (6db gain setting) (10) a ana in (sp) gain from ana in to sp+/? 6 to 15 db 4 steps of 3 db table 15: timing parameters symbol characteristic min (2) typ (1) max (2) units conditions
30 isd5008 product voice solutions in silicon? symbol characteristic min (2) typ (1) max (2) units conditions a ana in (aux out) gain from ana in to aux out ?4 to +5 db 4 steps of 3 db a ana in (ga) ana in gain accuracy ?0.5 +0.5 db (11) a ana in (gt) ana in gain tracking 0.1 db 1000 hz, +3 to ?40 db 0tlp input, 6db setting r ana in ana in input resistance 60 to 102 k ? see ra in figure 2 aux in (14) v aux in aux in input voltage 1.0 v peak-to-peak (0 db gain setting) v aux in (0tlp) aux in (0tlp) input voltage 694.2 mv peak-to-peak (0 db gain setting) (10) a aux in (ana out) gain from aux in to ana out 0 to 9 db 4 steps of 3db a aux in (ga) aux in gain accuracy ?0.5 +0.5 db (11) a aux in (gt) aux in gain tracking 0.1 db 1000 hz, +3 to ?40 db 0tlp input, 0db setting r aux in aux in input resistance 21 to 40 k ? see ra in figure 3 speaker outputs (14) v sphg sp+/? output voltage (high gain setting) 3.6 v peak-to-peak, differential load = 150 ?; opa1, opa0 = 01 r splg sp+/? output load imp. (low gain) 8 ? opa1, opa0 = 10 r sphg sp+/? output load imp. (high gain) 70 ? opa1, opa0 = 01 c sp sp+/? output load cap. 100 pf v spag sp+/? output bias voltage (analog ground) 1.2 vdc v spdco speaker output dc offset ?100 100 mvdc with ana in to speaker, ana in ac coupled to v ssa icn ana in/(sp+/?) ana in to sp+/? idle channel noise ?65 db speaker load = 150 ? (12)(13) c r t (sp+/?)/ana out sp+/? to ana out cross talk ?65 db 1khz 0tlp input to ana in, with mic+/? and aux in ac coupled to v ssa , and measured at ana out feedthrough mode (12) psrr power supply rejection ratio ?50 db measured with a 1khz,100 mvpp sine wave input at v cca and v ccd pins table 16: analog parameters
31 isd5008 product isd symbol characteristic min (2) typ (1) max (2) units conditions f r frequency response (300?3400 hz) ?0.25 +0.25 db with 0tlp input to ana in, 6db setting (12) p outlg power output (low gain setting) 23.5 mw rms differential load at 8 ? sinad sinad ana in to sp+/? 62.5 db 0tlp ana in input minimum gain, 150 ? load (12)(13) ana out (14) sinad sinad mic in to ana out +/- 62.5 db load = 5k ? (12)(13) sinad sinad aux in to ana out (0 to 9 db) 62.5 db load = 5k ? (12)(13) icn mic/ana out idle channel noise? microphone ?65 db load = 5k ? (12)(13) icn aux in/ana out idle channel noise? aux in (0 to 9 db) ?65 db load = 5k ? (12)(13) psrr (ana out) power supply rejection ratio -50 db measured with a 1khz, 100mvpp sine wave to v cca , v ccd pins v bias ana out+ and ana out? 1.2 vdc inputs ac coupled to v ssa v offset ana out+ to ana out? ?100 +100 mvdc inputs ac coupled to v ssa r l minimum load impedence 5k ? differential load f r frequency response (300?3400 hz) ?0.25 +0.25 db 0tlp input to mic+/- in feedthrough mode. 0tlp input to aux in in feedthrough mode (12) c r t ana out/(sp+/-) ana out to sp+/- cross talk ?65 db 1khz 0tlp output from ana out, with ana in ac coupled to v ssa , and measured at sp+/- (12) c r t ana out/aux out ana out to aux out cross talk ?65 db 1khz 0tlp output from ana out, with ana in ac coupled to v ssa , and measured at aux out(12) aux out (14) v aux out aux out?maximum output swing 1.0 vpp 5 k ? load r l minimum load impedence 5k ? c l maximum load capacitance 100 pf table 16: analog parameters
32 isd5008 product voice solutions in silicon? 1. typical values: t a = 25c and vcc = 3.0v. 2. all min/max limits are guaranteed by isd via electrical testing or characterization. not all specifications are 100 percent tested. 3. low-frequency cut off depends upon the value of external capacitors (see pin descriptions). 4. differential input mode. nominal differential input is 208 mvp-p. (0 dbm0) 5. sampling frequency can vary as much as ?6/+4 percent over the industrial temperature and voltage ranges. for greater stability, an external clock can be utilized (see pin descriptions). sampling frequency will be accurate within 1% for 5.3khz, and 5% for 4.0, 6.4 and 8.0 khz sampling rates at room temperature. 6. playback and record duration can vary as much as ?6/+4 percent over the industrial temperature and voltage ranges. for greater stability, an external clock can be utilized (see pin descriptions). playback and record durations are accurate within 1% for 5.3khz, and 5% for 4.0, 6.4 and 8.0khz sampling rates at room temperature. 7. filter specification applies to the low pass filter. therefore, from input to output, expect a 6 db drop by nature of passing through the filter twice. 8. for optimal signal quality, this maximum limit is recommended. 9. when a record command is sent, t rac = t rac + t raclo on the first row addressed. 10. the maximum signal level at any input is defined as 3.17db higher than the reference transmission level point. (0tlp) this is the point where signal clipping may begin. 11. measured at 0tlp point for each gain setting. see table 4 and table 5. 12. 0tlp is the reference test level through inputs and outputs. see table 4 and table 5. 13. referenced to 0tlp input at 1khz, measured over 300 to 3,400 hz bandwidth. 14. for die, only typical values from analog parameters are applicable. symbol characteristic min (2) typ (1) max (2) units conditions v bias aux out 1.2 vdc sinad sinad?ana in to aux out 62.5 db 0tlp ana in input, minimum gain, 5k load (12)(13) icn (aux out) idle channel noise? ana in to aux out ?65 db load = 5k ? (12)(13) c r t aux out/ana out aux out to ana out cross talk ?65 db 1 khz 0tlp input to ana in, with mic +/- and aux in ac coupled to v ssa , and measured at sp+/-, load = 5k ?. referenced to nominal 0tlp @ output volume control (14) a out output gain ?28 to 0 db 8 steps of 4 db, referenced to output gain accuracy -0.5 0.5 db ana in = 1 khz 0tlp, 6db gain setting, measured differentially at sp+/? table 16: analog parameters
33 isd5008 product isd table 17: spi ac parameters (1) 1. typical values: t a = 25c and v cc = 3.0 v. timing measured at 50 percent of the v cc level. 2. tristate test condition symbol characteristics min max units conditions t sss ss setup time 500 nsec t ssh ss hold time 500 nsec t dis data in setup time 200 nsec t dih data in hold time 200 nsec t pd output delay 500 nsec t df output delay to hiz 500 nsec (2) t ssmin ss high 1 sec t sckhi sclk high time 400 nsec t scklow sclk low time 400 nsec f 0 clk frequency 1,000 khz
34 isd5008 product voice solutions in silicon? 6timing diagrams figure 17: spi timing diagram figure 18: 8-bit spi command format
35 isd5008 product isd figure 19: 24-bit spi command format figure 20: playback/record and stop cycle ss mosi miso d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 c3 c4 c5 c6 c7 d0 d1 d2 d3 d4 d5 a4 a5 a6 a7 a8 a9 ovf eom a0 a1 a2 a3 a10 sclk byte 1 byte 2 byte 3 a11 a12 a13 a14 a15 xxxxxx c2 c1 c0
36 isd5008 product voice solutions in silicon? 7 device physical dimensions figure 21: 28-lead 8x13.4 mm plastic thin small outline package (tsop) type i (e) note: lead coplanarity to be within 0.004 inches. table 18: plastic thin small outline package (tsop) type i (e) dimensions inches millimeters min nom max min nom max a 0.520 0.528 0.535 13.20 13.40 13.60 b 0.461 0.465 0.469 11.70 11.80 11.90 c 0.311 0.315 0.319 7.90 8.00 8.10 d 0.002 0.006 0.05 0.15 e 0.007 0.009 0.011 0.17 0.22 0.27 f 0.0217 0.55 g 0.037 0.039 0.041 0.95 1.00 1.05 h036036 i 0.020 0.022 0.028 0.50 0.55 0.70 j 0.004 0.008 0.10 0.21
37 isd5008 product isd figure 22: 28-lead 0.600-inch plastic dual inline package (pdip) (p) table 19: plastic dual inline package (pdip) (p) dimensions inches millimeters min nom max min nom max a 1.445 1.450 1.455 36.70 36.83 36.96 b1 0.150 3.81 b2 0.065 0.070 0.075 1.65 1.78 1.91 c1 0.600 0.625 15.24 15.88 c2 0.530 0.540 0.550 13.46 13.72 13.97 d 0.19 4.83 d1 0.015 0.38 e 0.125 0.135 3.18 3.43 f 0.015 0.018 0.022 0.38 0.46 0.56 g 0.055 0.060 0.065 1.40 1.52 1.65 h 0.100 2.54 j 0.008 0.010 0.012 0.20 0.25 0.30 s 0.070 0.075 0.080 1.78 1.91 2.03 0 15 0 15
isd5008 product 38 voice solutions in silicon ? figure 23: 28-lead 0.300-inch plastic small outline integrated circuit (soic) (s) note: lead coplanarity to be within 0.004 inches. table 20: plastic small outline integrated circuit (soic) (s) dimensions inches millimeters min nom max min nom max a 0.701 0.706 0.711 17.81 17.93 18.06 b 0.097 0.101 0.104 2.46 2.56 2.64 c 0.292 0.296 0.299 7.42 7.52 7.59 d 0.005 0.009 0.0115 0.127 0.22 0.29 e 0.014 0.016 0.019 0.35 0.41 0.48 f 0.050 1.27 g 0.400 0.406 0.410 10.16 10.31 10.41 h 0.024 0.032 0.040 0.61 0.81 1.02
isd5008 product 39 isd figure 24: isd5008 series bonding physical layout (1) (unpackaged die) 1. the backside of die is internally connected to v ss . it must not be connected to any other potential or damage may occur. 2. double bond recommended. 3. this figure reflects the current die thickness. please contact isd as this thickness may change in the future. isd5008 series i. die dimensions x: 166.5 1 mils y: 302.4 1 mils ii. die thickness (3) 11.5 1.0 mils iii. pad opening (min) 90 x 90 microns 3.5 x 3.5 mils v ssd isd5008 v ssa v ssa mic+ aux in ana in anaout+ mic? v ssa (2) anaout? acap auxout sp? v cca (2) sp+ rac v ssd miso mosi ss sclk v ccd v ccd int xclk
isd5008 product 40 voice solutions in silicon ? table 21: isd5008 series device pin/pad designations, with respect to die center (m) 1. double bond recommended. pin pin name xaxis yaxis v ssd v ss digital power supply ?1837.0 3623.7 v ssd v ss digital power supply ?1665.4 3623.7 miso master in slave out ?1325.7 3623.7 mosi master out slave in ?1063.8 3623.7 ss slave select ?198.2 3623.7 sclk slave clock ?14.8 3623.7 v ccd v cc digital power supply 169.4 3623.7 v ccd v cc digital power supply 384.8 3623.7 xclk external clock input 564.7 3623.7 int interrupt 794.7 3623.7 rac row address clock 1483.7 3623.7 v ssa v ss analog power supply 1885.1 3623.7 v ssa v ss analog power supply ?1943.2 ?3615.9 mic+ noninverting microphone input ?1735.4 ?3615.9 mic? inverting microphone input ?1502.9 ?3615.9 ana out+ noninverting analog output ?1251.2 ?3615.9 ana out ? inverting analog output ?917.0 ?3615.9 acap agc/automute cap ?632.6 ?3615.9 sp? inverting speaker output ?138.4 ?3615.9 v ssa (1) v ss analog power supply 240.2 ?3615.9 sp+ noninverting speaker output 618.8 ?3615.9 v cca (1) v cc analog power supply 997.4 ?3615.9 ana in analog input 1249.9 ?3615.9 aux in auxiliary input 1515.5 ?3615.9 aux out auxiliary output 1758.4 ?3615.9
isd5008 product 41 isd figure 25: sd5008 chip scale package (csp) (z ) table 22: csp dimensions (mm) e top view bottom view g f e i h c aa 2 a 1 b side view a5 a4 a3 b5 b4 b3 b2 c5 c4 c3 c2 d5 d4 d3 d2 e5 e4 e3 e2 a1 ball corner d a2 a1 b1 c1 d1 e1 symbol min. nom. max. a??0.86 a 1 0.18 ? ? a 2 ?0.55? b 0.30 0.35 0.40 c?4.68? d?8.13? e0.75 f?3.00? g?0.84? h?2.57? i?3.00? pin name ball location mic- a1 acap a2 v ssa a3 v cca a4 aux in a5 mic+ b1 ana out- b2 sp- b3 ana in b4 aux out b5 v ssa c1 ana out + c2 sp+ c3 v ccd c4 v ssa c5 v ssd d1 miso d2 ss d3 xclk d4 rac d5 vssd e1 mosi e2 sclk e3 vccd e4 int e5
isd5008 product 42 voice solutions in silicon ? 8 ordering information when ordering isd5008 series devices, please refer to the following valid part numbers. for the latest product information, access isd?s worldwide website at http://www.isd.com. part number isd5008e isd5008ed isd5008ei isd5008p isd5008s isd5008sd isd5008si isd5008x ISD5008Z ISD5008Zd ISD5008Zi product family isd5008 product (4 to 8 minute durations) special temperature field: blank = commercial packaged (0c to +70c) or commercial die (0c to +50c) d = extended (?20c to +70c) i = industrial (?40c to +85c) package type: e = 28-lead 8x13.4mm plastic thin small outline package (tsop) type 1 p = 28-lead 0.600-inch plastic dual inline package (pdip) s = 28-lead 0.300-inch plastic small outline package (soic) x =die z = chip scale package (csp) isd5008?_ _ isd part number description
isd5008 product 43 isd
part no. isd5008pds1-799 2727 north first street san jose, california 95134 tel: 408/943-6666 fax: 408/544-1787 http://www.isd.com important notices the warranty for each product of isd (information storage devices, inc.), is contained in a written warranty which governs sale and use of such product. such warranty is contained in the printed terms and conditions under which such product is sold, or in a separate written warranty supplied with the product. please refer to such written warranty with respect to its applicability to certain applications of such product. these products may be subject to restrictions on use. please contact isd for a list of the current additional restrictions on these products. by purchasing these products, the purchaser of these products agrees to comply with such use restrictions. please contact isd for clarification of any restrictions described herein. isd, reserves the right, without further notice, to change the isd chipcorder product specifications and/or information in this document and to improve reliability, functions and design. isd assumes no responsibility or liability for any use of the isd chipcorder product. isd conveys no license or title, either expressed or implied, under any patent, copyright, or mask work right to the isd chipcorder product, and isd makes no warranties or representations that the isd chipcorder product are free from patent, copyright, or mask work right infringement, unless otherwise specified. application examples and alternative uses of any integrated circuit contained in this publication are for illustration purposes only and isd makes no representation or warranty that such applications shall be suitable for the use specified. the 100-year retention and 100k record cycle projections are based upon accelerated reliability tests, as published in the isd reliability report, and are neither warranted nor guaranteed by isd. information contained in this isd chipcorder data sheet supersedes all data for the isd chipcorder product published by isd prior to october, 1999. this data sheet and any future addendum to this data sheet is (are) the complete and controlling isd chipcorder product specifications. in the event any inconsistencies exist between the information in this and other product documentation, or in the event that other product documentation contains information in addition to the information in this, the information contained herein supersedes and governs such other information in its entirety. copyright? 1999, isd (information storage devices, inc.) all rights reserved. isd is a registered trademark of isd. chipcorder is a trademark of isd. all other trademarks are properties of their respective owners.

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